CCD image sensors typically include an array of photosensitive areas (or “pixels”) that collect charge carriers in response to illumination. The collected charge is subsequently transferred from the array of pixels and converted to a voltage from which an image may be reconstructed by associated circuitry. FIG. 1A depicts a conventional interline CCD image sensor 10 that contains an array of photodiodes 11 arranged in columns. A vertical CCD (VCCD) 12 is disposed next to each column of photodiodes 11, and the VCCDs 12 are connected to a horizontal CCD (HCCD) 13. Each photodiode 11 along with its corresponding portion of VCCD 12 constitutes a pixel of the image sensor 10. Following an exposure period, charge is transferred from the photodiodes 11 into the VCCDs 12, which subsequently shift the charge, row-by-row in parallel, into the HCCD. The HCCD then transfers the charge serially to output circuitry 14 that includes, e.g., a floating diffusion sense node and an output buffer amplifier. The charge from the HCCD is converted, pixel-by-pixel, into voltage at the output circuitry 14, and the signal is then transferred to additional circuitry (either on-chip or off-chip) for reconstruction into an image.
FIG. 1B illustrates a portion of a conventional output channel for sampling a charge packet with two different gains. The output channel includes a CCD shift register (e.g., an HCCD) and CCD gates 140 and 145. FIG. 1B depicts the CCD shift register as a pseudo-two-phase CCD shift register, but the CCD shift register may be implemented as, e.g., a two-phase, three-phase, or four-phase CCD shift register, details of which are known in the art and therefore not described in detail. The charge packets are transferred from right to left (in the direction of arrow 150) through the CCD shift register by the complementary clocking of CCD gates 140, 145. Each charge packet transfers through an output gate 135 to a sense node 125 at the end of the CCD shift register. The sense node 125 is connected to the gate of a transistor (or an “amplification circuit”) 130. Sense node 125 and amplification circuit 130 are implemented, e.g., as a floating diffusion and source follower transistor, respectively.
Current sink 131 is the load for the source node of transistor 130. The drain node of transistor 130 is connected to power supply 133. Output signal line 132 is an output of the amplification circuit 130. Reset transistors 110, 120 control the capacitance of the sense node 125. The two reset transistors allow for two different charge-to-voltage conversion gains (high and low) of the amplification circuit 130.
The charge-sampling technique for high gain holds the reset transistor 110 continuously in the on state. To sample one charge packet, the reset transistor 120 is pulsed on and then off to reset the voltage of the sense node 125. The voltage of the sense node 125 is equal to the voltage of diffusion region 105. A reset level (VRH) is sampled on the output signal line 132 of the amplification circuit 130. Next, a charge packet is transferred from the CCD shift register, through the output gate 135, to the sense node 125. A signal level (VSH) is then sampled on the output signal line 132. The magnitude of the charge packet is represented by the difference between the signal level sampled at high gain and the reset level sampled at high gain (VSH−VRH).
The charge-sampling technique for low gain holds the reset transistor 120 continuously in the on state. When reset transistor 120 is on, the sense node 125 expands to include both diffusion region 115 and sense node 125. This adds capacitance to the amplification circuit 130. The additional capacitance reduces the voltage change caused by transferring a charge packet onto the sense node 125. To sample one charge packet, the reset transistor 110 is pulsed on and then off to reset the voltage of the combined sense node 125 and diffusion region 115. The voltage of the combined sense node 125 and diffusion region 115 is equal to the voltage of the diffusion region 105. A reset level (VRL) is sampled on the output signal line 132 of the amplification circuit 130. Next, a charge packet is transferred from the CCD shift register, through the output gate 135, to the combined sense node 125 and diffusion region 115. A signal level (VSL) is then sampled on the output signal line 132. The magnitude of the charge packet is represented by the different between the signal level sampled at low gain and the reset level sampled at low gain (VSL−VRL).
The capacitance added by diffusion region 115 may be just the diffusion region capacitance itself, or it may include additional capacitance from a capacitor formed by a gate or plates of metal. Such conventional techniques for sampling a charge packet with high or low gain may involve a noise penalty. The amplification circuit 130 has its own gate dimensions, width W and length L, which are typically optimized for lowest noise performance in the high-gain mode. As known to those of skill in the art, the width and length of the gate of the amplification circuit 130 as well as the thickness of the gate oxide have an impact on the noise of the transistor. When the capacitance of diffusion region 115 is added to the capacitance of the sense node 125, charge-to-voltage noise will result unless the transistor 130 gate width, length, and gate oxide thickness are optimized for the additional capacitance—which, typically, they are not. Thus, there is a need for image sensor designs enabling charge sampling at different gains without concomitant conversion-noise penalties.